1. Field of the Invention
This invention relates to semiconductor devices and particularly to erasable programmable flash memory devices.
2. Description of Related Art
Holes induced by source erase cause a reliability problem in Flash memory devices. Although use of negative gate source erase alleviates hot hole injection, the problem is that it does not eliminate hot hole generation.
U.S. Pat. No. 5,395,773 of Ravindhran et al. shows a MOSFET with a gate penetrating halo implant. However, the halo implant is below the source/drain (S/D) regions and is for a different purpose from the halo ion implant of the invention.
An advantage of this invention is that a surface halo source structure is used in which an N-type region surrounds a P-type region forming a combined P-type/N-type source region. The result is provision of a channel erase function performed at the same bias voltage as the source erase, which eliminates hole injection and hole generation. Thus channel erase can be achieved with a bias condition similar to source erase. Hot hole injection can be eliminated due to the employment of channel erase.
In accordance with this invention, a Flash EEPROM memory device includes a gate electrode stack formed on the surface of a doped silicon semiconductor substrate and, a source region and a drain region formed in the surface of the doped silicon semiconductor substrate. The device includes a surface halo formed in the surface of the source region juxtaposed with the gate electrode stack without any halo region in the surface of the drain region. Thus, an asymmetric device is provided with the halo region separated from the semiconductor substrate by intervening portions of the source region. Preferably, the source region and the drain region are located in the surface of the substrate, with the source region and the drain region being located aside from the gate electrode stack in overlapping relationship with the gate electrode stack. In addition, a surface halo region is formed in the surface of the source region surrounded by the source region and juxtaposed with the gate electrode stack and with a slight overlap in position of the halo region with the gate electrode stack.
Preferably, a contact region is doped with P type boron dopant with a dose from about 5 E 14 ions/cm2 to about 5 E 15 ions/cm2. The contact region is formed in the doped silicon semiconductor material.
The P type BF2 dopant was ion implanted into a P+ type halo region with a dose from about 5 E 14 ions/cm2 to about 5 E 15 ions/cm2, at an energy from about 10 keV to about 30 keV. The tunnel oxide layer has a thickness from about 70 xc3x85 to about 120 xc3x85.
The device is erased with a negative voltage from about xe2x88x9210 Volts to about xe2x88x9215 Volts on the control gate electrode and a positive voltage from about 10 Volts to about 5 Volts on the source region.
The device is erased with voltages applied during the erase mode as follows: